As the density of integrated circuits has increased in recent years, the demand for lower power circuit elements has also increased in order to lower overall power consumption and improve heat dissipation. Standby power consumption in conventional TTL and CMOS circuits is generally relatively low. Typically, TTL logic gates are fabricated with bipolar transistors that source or sink current to a resistance load which, in a static mode, have a defined standby current. CMOS circuits, on the other hand, are configured of complementary P- and N- channel transistors wherein the P-channel transistor is operable to pull a node high and the N-channel transistor is operable to pull the node low. However, with a CMOS circuit, the P-channel transistor is turned off when the N-channel transistor is turned on, thus drawing minimal current from the power supply in a static mode. Therefore, CMOS circuits result in considerably less current drain on the power supply as compared to TTL circuits.
Although CMOS circuits result in significantly lower current drain on a power supply, recent industry demands for battery protected circuitry has required even lower current drain. For example, some battery backed up circuitry must have battery lifetimes that exceed ten years with extremely small current drains. Although a CMOS circuit in the static condition draws minimal current, a problem does exist during switching between logic states. The current draw due to switching the CMOS circuit is the result of the transition of the gate voltage on the complementary pair wherein one transistor in the pair is turned on prior to the other transistor being turned off during this transition.
For example, when the N-channel transistor is initially on, as the result of a high gate voltage, switching of the gate voltage to a low voltage will turn on the P-channel transistor and turn off the N-channel transistor. As the gate voltage goes negative, the P-channel transistor is turned on when the gate voltage is one V.sub.T less than the source voltage. However, this voltage may still be greater than one V.sub.T above the source of the N-channel transistor and, therefore, the N-channel transistor will continue to draw current through the P-channel transistor. As the gate voltage falls below the V.sub.T of the N-channel transistor, the N-channel transistor turns off. Therefore, when the voltage on the gates of the complementary pair is between one V.sub.T below the source of the P-channel transistor and one V.sub.T above the source of the N-channel transistor, current is conducted through the pair. For extremely low current drain applications such as battery backed up parts, this current drain can be considerable during the switching of the gate. Further, for very low slew rate input signals, this situation can be exacerbated. Therefore, conventional CMOS circuits utilized in buffers and inverters have significant disadvantages in low-current applications, especially for low slew rate input signals. There therefore exists the need for improvements in CMOS circuitry utilized to buffer or invert low slew rate signals to minimize the current drain during switching.